371 lines
13 KiB
C
371 lines
13 KiB
C
/* Author: Musa Mahmood - JIIM, Inc.
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* Date: 11/11/2023
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* License: This is proprietary code and may not be used without express written permission.
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*/
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#include "ads1298.h"
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#include "app_util_platform.h"
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#include "nrf_delay.h"
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#include "app_error.h"
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#include "nrf_log.h"
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#include "nrf_log_ctrl.h"
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#include "nrf_log_default_backends.h"
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#include "nrf_gpio.h"
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#include "nrf_drv_gpiote.h"
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#include <string.h>
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//#include "usb_logging.h"
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uint8_t ads1298_default_regs[] = {
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ADS1298_REGDEFAULT_CONFIG1,
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ADS1298_REGDEFAULT_CONFIG2,
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ADS1298_REGDEFAULT_CONFIG3,
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ADS1298_REGDEFAULT_LOFF,
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ADS1298_REGDEFAULT_CH1SET,
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ADS1298_REGDEFAULT_CH2SET,
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ADS1298_REGDEFAULT_CH3SET,
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ADS1298_REGDEFAULT_CH4SET,
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ADS1298_REGDEFAULT_CH5SET,
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ADS1298_REGDEFAULT_CH6SET,
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ADS1298_REGDEFAULT_CH7SET,
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ADS1298_REGDEFAULT_CH8SET,
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ADS1298_REGDEFAULT_RLD_SENSP,
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ADS1298_REGDEFAULT_RLD_SENSN,
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ADS1298_REGDEFAULT_LOFF_SENSP,
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ADS1298_REGDEFAULT_LOFF_SENSN,
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ADS1298_REGDEFAULT_LOFF_FLIP,
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ADS1298_REGDEFAULT_LOFF_STATP,
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ADS1298_REGDEFAULT_LOFF_STATN,
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ADS1298_REGDEFAULT_GPIO,
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ADS1298_REGDEFAULT_PACE,
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ADS1298_REGDEFAULT_RESP,
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ADS1298_REGDEFAULT_CONFIG4,
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ADS1298_REGDEFAULT_WCT1,
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ADS1298_REGDEFAULT_WCT2
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};
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// SPI flags:
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static volatile bool spi_xfer_done;
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static uint8_t rx_buffer[27+2];
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// SPI Instance:
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static const nrf_drv_spi_t spi0 = NRF_DRV_SPI_INSTANCE(0);
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// SPI Event Handler:
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static void spi_event_handler(nrf_drv_spi_evt_t const *p_event, void *p_context)
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{
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spi_xfer_done = true;
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#if ADS1298_LOG_DEBUG
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NRF_LOG_DEBUG("SPI transfer completed.");
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#endif
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}
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void ads1298_initialize(ble_exg_t *p_exg, ads1298_info_t *p_info) {
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NRF_LOG_INFO("Initializing ADS1298...");
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// 1. Power up the ADS1298:
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ads1298_power_up();
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#if ADS1298_LOG_DEBUG
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NRF_LOG_FLUSH();
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#endif
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nrf_drv_spi_config_t spi_config;
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memset(&spi_config, 0, sizeof(spi_config));
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// 2. Initialize SPI
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spi_config.bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST;
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spi_config.ss_pin = ADS1298_CS_PIN;
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spi_config.miso_pin = ADS1298_MISO_PIN;
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spi_config.mosi_pin = ADS1298_MOSI_PIN;
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spi_config.sck_pin = ADS1298_SCK_PIN;
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spi_config.frequency = NRF_DRV_SPI_FREQ_2M;
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spi_config.irq_priority = APP_IRQ_PRIORITY_HIGHEST;
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spi_config.mode = NRF_DRV_SPI_MODE_1;
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spi_config.orc = 0x55;
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APP_ERROR_CHECK(nrf_drv_spi_init(&spi0, &spi_config, spi_event_handler, NULL));
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// 3. Stop read data continuous mode (rdatac)
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ads1298_stop_rdatac();
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#if ADS1298_LOG_DEBUG
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NRF_LOG_FLUSH();
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#endif
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// 4. Init registers:
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// Copy default registers into p_exg->ads1298_settings (first 25 bytes)
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memset(p_exg->ads1298_settings, 0, ADS1298_SETTINGS_SIZE);
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memcpy(p_exg->ads1298_settings, ads1298_default_regs, ADS1298_REGISTER_COUNT);
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ads1298_init_default_registers();
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#if ADS1298_LOG_DEBUG
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NRF_LOG_FLUSH();
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#endif
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// 5. Soft start:
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ads1298_soft_start_conversion();
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// 6. Check ID: (sets lower 3 bits of ads1298_settings[25])
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ads1298_check_id(p_exg, p_info);
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// 7. Start read data continuous mode (rdatac):
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ads1298_start_rdatac();
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// 8. Place on standby mode:
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ads1298_standby();
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// 9. Set remainder of ads1298_settings[25]:
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p_exg->ads1298_settings[25] |= 0x80; // 16-bit mode
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// ads1298_settings[25] &= 0b10011111; // TODO: sets downsample to zero
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#if ADS1298_LOG_DEBUG
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NRF_LOG_FLUSH();
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#endif
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}
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void ads1298_uninitialize(void) {
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NRF_LOG_INFO("Uninitializing ADS1298...");
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nrf_drv_spi_uninit(&spi0);
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}
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bool ads1298_check_id(ble_exg_t *p_exg, ads1298_info_t *p_info) {
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bool device_found = false;
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#if ADS1298_LOG_DEBUG
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NRF_LOG_INFO("Checking ADS129xR? ID:");
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#endif
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uint8_t tx_buf[6] = {ADS1298_OPC_RREG|ADS1298_REGADDR_ID, 0x01, 0, 0, 0, 0};
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uint8_t rx_buf[6] = {0,0,0,0,0,0};
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, tx_buf, 2, rx_buf, 6));
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while(!spi_xfer_done) {
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__WFE();
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}
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#if ADS1298_LOG_DEBUG
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NRF_LOG_INFO("rx_buf[3] = 0x%X", rx_buf[3]);
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NRF_LOG_INFO("rx_buf dump:");
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NRF_LOG_HEXDUMP_INFO(rx_buf, 6);
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#endif
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// Check lower 3 bits 0x[...]..[???]
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uint8_t nch_check = rx_buf[3] & 0x07; // 0x.....111
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p_exg->ads1298_settings[25] |= nch_check;
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p_info->nChs = 0;
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if (nch_check == ADS129x_4CH_BITMASK) {
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p_info->nChs = 4; // ADS1294
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} else if (nch_check == ADS129x_6CH_BITMASK) {
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p_info->nChs = 6; // ADS1296
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} else if (nch_check == ADS129x_8CH_BITMASK) {
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p_info->nChs = 8; // ADS1298
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} else {
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NRF_LOG_ERROR("Expected ADS129xX not detected! E0");
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return false;
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}
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// Check middle bits 0x[...]10[...] < always should be 10
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if ((rx_buf[3] & 0x10) != 0x10 || p_info->nChs == 0) {
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NRF_LOG_ERROR("Expected ADS129xX not detected! E1");
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return false;
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}
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// Check first three bits: 0x[???]..[...]
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uint8_t r_ver_chk = rx_buf[3] & 0xE0;
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if (r_ver_chk == ADS129x_DEVICE_FAMILY_BITMASK) {
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p_info->name_len = sprintf(p_info->name, "ADS129%d", p_info->nChs);
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NRF_LOG_INFO("%s detected! (name_len: %d)", p_info->name, p_info->name_len);
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device_found = true;
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p_exg->ads1298_settings[25] &= (~0x08);
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} else if (r_ver_chk == ADS129xR_DEVICE_FAMILY_BITMASK) {
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p_info->name_len = sprintf(p_info->name, "ADS129%dR", p_info->nChs);
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NRF_LOG_INFO("%s detected! (name_len: %d)", p_info->name, p_info->name_len);
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p_exg->ads1298_settings[25] |= 0x08;
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device_found = true;
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} else {
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NRF_LOG_ERROR("Expected ADS129xX not detected! E2");
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return false;
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}
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return device_found;
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}
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// chNumber = 1:8
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__STATIC_INLINE bool ads1298_check_channel(ads1298_info_t *p_info, uint8_t chNumber) {
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if (chNumber > p_info->nChs) return false;
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if (chNumber > 8) {
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NRF_LOG_INFO("[ads1298_check_channel] INVALID CHANNEL NUMBER: %d!", chNumber);
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return false;
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}
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return !((p_info->registers[3 + chNumber] & 0x80) == 0x80);
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}
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void ads1298_update_active_chs(ads1298_info_t *p_info) {
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p_info->active_chs = 0;
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if (ads1298_check_channel(p_info, 1)) p_info->active_chs |= 0x80;
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if (ads1298_check_channel(p_info, 2)) p_info->active_chs |= 0x40;
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if (ads1298_check_channel(p_info, 3)) p_info->active_chs |= 0x20;
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if (ads1298_check_channel(p_info, 4)) p_info->active_chs |= 0x10;
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if (p_info->nChs == 4) return;
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if (ads1298_check_channel(p_info, 5)) p_info->active_chs |= 0x08;
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if (ads1298_check_channel(p_info, 6)) p_info->active_chs |= 0x04;
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if (p_info->nChs == 6) return;
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if (ads1298_check_channel(p_info, 7)) p_info->active_chs |= 0x02;
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if (ads1298_check_channel(p_info, 8)) p_info->active_chs |= 0x01;
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}
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void ads1298_update_registers(ads1298_info_t *p_info) {
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NRF_LOG_INFO("Updating ADS1298 registers...");
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ads1298_update_active_chs(p_info);
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uint8_t i = 0; // Register index
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uint8_t tx_data[ADS1298_REGISTER_COUNT + 2]; // plus 2 for opcodes
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uint8_t rx_data[ADS1298_REGISTER_COUNT + 2];
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memset(tx_data, 0, ADS1298_REGISTER_COUNT + 2);
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memset(rx_data, 0, ADS1298_REGISTER_COUNT + 2);
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// Write Register Opcode | Register Address:
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tx_data[0] = ADS1298_OPC_WREG | ADS1298_REGADDR_CONFIG1;
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tx_data[1] = ADS1298_REGISTER_COUNT;
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// Copy default register values:
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memcpy(&tx_data[2], p_info->registers, ADS1298_REGISTER_COUNT);
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// Transaction size = 2 + number of registers to write
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, tx_data, ADS1298_REGISTER_COUNT + 2, rx_data, ADS1298_REGISTER_COUNT + 2));
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while (!spi_xfer_done)
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{
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__WFE();
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}
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#if ADS1298_LOG_DEBUG
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NRF_LOG_INFO("[ADS1298] Registers updated!");
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#endif
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}
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void ads1298_init_default_registers(void) {
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NRF_LOG_INFO("Initializing ADS1298 registers...");
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uint8_t i = 0; // Register index
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uint8_t tx_data[ADS1298_REGISTER_COUNT + 2]; // plus 2 for opcodes
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uint8_t rx_data[ADS1298_REGISTER_COUNT + 2];
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memset(tx_data, 0, ADS1298_REGISTER_COUNT + 2);
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memset(rx_data, 0, ADS1298_REGISTER_COUNT + 2);
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// Write Register Opcode | Register Address:
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tx_data[0] = ADS1298_OPC_WREG | ADS1298_REGADDR_CONFIG1;
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tx_data[1] = ADS1298_REGISTER_COUNT;
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// Copy default register values:
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memcpy(&tx_data[2], ads1298_default_regs, ADS1298_REGISTER_COUNT);
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// Transaction size = 2 + number of registers to write
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, tx_data, ADS1298_REGISTER_COUNT + 2, rx_data, ADS1298_REGISTER_COUNT + 2));
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while (!spi_xfer_done)
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{
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__WFE();
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}
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#if ADS1298_LOG_DEBUG
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NRF_LOG_INFO("[ADS1298] Registers initialized.");
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#endif
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}
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// Power controls:
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void ads1298_power_down(void) {
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nrf_gpio_pin_clear(ADS1298_PWDN_PIN);
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nrf_delay_ms(5);
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}
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void ads1298_power_up(void) {
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nrf_gpio_pin_set(ADS1298_PWDN_PIN);
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nrf_delay_ms(80);
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}
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// Standby/Wakeup controls:
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void ads1298_wakeup(void) {
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NRF_LOG_INFO("Waking up ADS1298...");
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uint8_t cmd = ADS1298_OPC_WAKEUP;
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uint8_t rx_buf;
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, &cmd, 1, &rx_buf, 1));
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while (!spi_xfer_done)
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{
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__WFE();
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}
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}
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void ads1298_standby(void) {
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NRF_LOG_INFO("Placing ADS1298 in standby mode...");
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uint8_t cmd = ADS1298_OPC_STANDBY;
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uint8_t rx_buf;
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, &cmd, 1, &rx_buf, 1));
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while (!spi_xfer_done)
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{
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__WFE();
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}
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}
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// Start/stop conversions
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void ads1298_soft_start_conversion(void) {
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NRF_LOG_INFO("[ADS1298] Starting conversion...");
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uint8_t cmd = ADS1298_OPC_START;
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uint8_t rx_buf;
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, &cmd, 1, &rx_buf, 1));
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while (!spi_xfer_done)
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{
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__WFE();
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}
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}
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void ads1298_start_rdatac(void) {
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NRF_LOG_INFO("[ADS1298] Starting Read Data Continuous Mode...");
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uint8_t cmd = ADS1298_OPC_RDATAC;
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uint8_t rx_buf;
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, &cmd, 1, &rx_buf, 1));
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while (!spi_xfer_done)
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{
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__WFE();
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}
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}
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void ads1298_stop_rdatac(void) {
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NRF_LOG_INFO("[ADS1298] Stopping Read Data Continuous Mode...");
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uint8_t cmd = ADS1298_OPC_SDATAC;
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uint8_t rx_buf;
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spi_xfer_done = false;
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APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi0, &cmd, 1, &rx_buf, 1));
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while (!spi_xfer_done)
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{
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__WFE();
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}
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}
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// __STATIC_INLINE uint8_t get_channel_count_from_settings(uint8_t settings) {
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// uint8_t lower_bits = settings & 0x07;
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// if (lower_bits == ADS129x_4CH_BITMASK) {
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// return 4;
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// } else if (lower_bits == ADS129x_6CH_BITMASK) {
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// return 6;
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// } else if (lower_bits == ADS129x_8CH_BITMASK) {
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// return 8;
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// }
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// }
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// TODO: Add option for 2 bytes (low resolution)
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__STATIC_INLINE void copy_relevant_data(ble_exg_t *p_exg, uint8_t active_chs/*, bool hi_res*/) {
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if ((active_chs & 0x80) == 0x80) memcpy(&p_exg->exg_ch1_buffer[p_exg->data_buffer_count], &rx_buffer[3], 3);
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if ((active_chs & 0x40) == 0x40) memcpy(&p_exg->exg_ch2_buffer[p_exg->data_buffer_count], &rx_buffer[6], 3);
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if ((active_chs & 0x20) == 0x20) memcpy(&p_exg->exg_ch3_buffer[p_exg->data_buffer_count], &rx_buffer[9], 3);
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if ((active_chs & 0x10) == 0x10) memcpy(&p_exg->exg_ch4_buffer[p_exg->data_buffer_count], &rx_buffer[12], 3);
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if ((active_chs & 0x08) == 0x08) memcpy(&p_exg->exg_ch5_buffer[p_exg->data_buffer_count], &rx_buffer[15], 3);
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if ((active_chs & 0x04) == 0x04) memcpy(&p_exg->exg_ch6_buffer[p_exg->data_buffer_count], &rx_buffer[18], 3);
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if ((active_chs & 0x02) == 0x02) memcpy(&p_exg->exg_ch7_buffer[p_exg->data_buffer_count], &rx_buffer[21], 3);
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if ((active_chs & 0x01) == 0x01) memcpy(&p_exg->exg_ch8_buffer[p_exg->data_buffer_count], &rx_buffer[24], 3);
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p_exg->data_buffer_count += 3;
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}
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// Buffer size depends on version (27 bytes for ADS1298, 21 for ADS1296, and 15 for ADS1294)
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void ads1298_get_data(ble_exg_t *p_exg, uint8_t active_chs) {
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spi_xfer_done = false;
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memset(rx_buffer, 0, 27);
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nrf_drv_spi_transfer(&spi0, rx_buffer, 27, rx_buffer, 27);
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while (!spi_xfer_done) { __WFE(); }
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copy_relevant_data(p_exg, active_chs);
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}
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void ads1296_get_data(ble_exg_t *p_exg, uint8_t active_chs) {
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spi_xfer_done = false;
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memset(rx_buffer, 0, 21);
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nrf_drv_spi_transfer(&spi0, rx_buffer, 21, rx_buffer, 21);
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while (!spi_xfer_done) { __WFE(); }
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copy_relevant_data(p_exg, active_chs);
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}
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void ads1294_get_data(ble_exg_t *p_exg, uint8_t active_chs) {
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spi_xfer_done = false;
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memset(rx_buffer, 0, 15);
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nrf_drv_spi_transfer(&spi0, rx_buffer, 15, rx_buffer, 15);
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while (!spi_xfer_done) { __WFE(); }
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// Check mode p_exg->ads1298_settings[26] b0
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copy_relevant_data(p_exg, active_chs);
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}
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